1. Field of the Invention
The present invention relates to a semiconductor memory device in which current consumption is reduced in a read operation, and more specifically, to a semiconductor memory device in which the current consumed in a column address counter and a latch in the read operation can be reduced.
2. Discussion of Related Art
FIG. 1 is a functional block diagram illustrating the configuration of a DDR SDRAM in the prior art.
A control logic 10 includes a command decoder 20 and a mode register 30. A clock enable signal CKEn, a clock signal CK, a clock bar signal /CK, a chip select signal /CSn, a write enable signal /WE, a column address strobe signal /CAS and a row address strobe signal /RAS are input to the control logic 10. Further, block select addresses BA0, BA1 and addresses A0 to A13 are input to the control logic 10 through an address register 40. The command decoder 20 generates read, write and precharge commands, etc. according to an input signal. The mode register 30 generates a CAS latency value and a burst length value according to an input address. A row address multiplexer 60 generates a row address according to an input address and also generates the row address according to an address outputted from a refresh counter 50.
A bank row address latch and decoder 90 outputs a bank select signal for selecting a memory bank, and is controlled by means of a bank control logic 70. A column decoder 130 generates a column address according to input addresses. A column address counter and latch 80 generates a plurality of column addresses for a burst operation if an address is received, and provides the generated column addresses to the column decoder 130. The column address counter and latch 80 also generates a signal col0 that divides even and odd regions of a memory bank. A bank memory array 100 is composed of a plurality of memory banks. The memory banks are selected according to a bank select signal. Each of the memory banks consists of a plurality of cells, which are selected according to a row address and a column address. A I/O gating DM mask logic 120 controls the input of data to the memory banks. Data write is controlled according to a data mask signal.
The data of the memory banks are amplified in a sense amplifier 110 and then latched in a read latch 140 via the I/O gating DM mask logic 120. The data latched in the read latch 140 is transferred to a driver 170 according to the operation of a multiplexer 150. The data is synchronized to DQS data from a DQS generator 180 and then outputted to an external chipset.
The data from the external chipset is input to a receiver 200 in synchronism with external DQS data. The data from the receiver 200 is stored in an input register 210 and input to the write FIFO and driver 190. The data from the write FIFO and driver 190 is written into a corresponding cell through the I/O gating DM mask logic 120 and the sense amplifier 110 according to a mask signal. Meanwhile, a clock CLK is applied to the driver 170 through a delay lock loop (DLL) 160.
The DDR SDRAM constructed above needs a column address counter because there exists a burst operation in the read and write operations. The column address counter operates in accordance with a timing at which the sense amplifier reads or writes data. That is, in the read operation, the column address counter operates at a clock to which a read command is applied. In the write operation, it operates after 2*tCK since a write command is applied. This is because 1*tCK is needed to align internal data, as can be seen from FIG. 2. In the DDR SDRAM, write data are applied later than the write command. It is also required that data latched at the rising edge of DQS be aligned at the falling edge of DQS, as shown in FIG. 2. In other words, a data D0 is latched at a first rising edge of DQS, and the data D0 is aligned while a data D1 is latched at a first falling edge of DQS. In the similar manner, a data D2 is latched at a second rising edge of DQS, and the data D2 is aligned while a data D3 is latched at a second falling edge of DQS. Accordingly, the fastest time point where data can be written in the sense amplifier is after 2*tCK from write. Therefore, in the write operation, all of the write command, the bank address and the column address have to be delayed as much as 2*tCK. A circuit for such delay is provided in the column address counter and latch 80. In the prior art, such a delay circuit is driven even in the read operation. Thus, lots of power is consumed.